MC9S12E128CFUE Datasheet, PDF (136/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 3 Port Integration Module (PIM9E128V1)
3.3.1.8 Port AD Interrupt Flag Register (PIFAD)
R
W
Reset
7
PIFAD15
0
6
PIFAD14
0
5
PIFAD13
0
4
PIFAD12
0
3
PIFAD11
0
2
PIFAD10
0
1
PIFAD9
0
0
PIFAD8
0
R
W
Reset
7
PIFAD7
0
6
PIFAD6
5
PIFAD5
4
PIFAD4
3
PIFAD3
2
PIFAD2
0
0
0
0
0
Figure 3-9. Port AD Interrupt Flag Register (PIFAD)
1
PIFAD1
0
0
PIFAD0
0
Read: Anytime. Write: Anytime.
Each flag is set by an active edge on the associated input pin. The active edge could be rising or falling
based on the state of the corresponding PPSADx bit. To clear each flag, write “1” to the corresponding
PIFADx bit. Writing a “0” has no effect.
NOTE
If the ATDDIEN0(1) bit of the associated pin is set to 0 (digital input buffer
is disabled), active edges can not be detected.
Table 3-8. PIFAD Field Descriptions
Field
Description
15:0 Interrupt Flags Port AD
PIFAD[15:0] 0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.
MC9S12E128 Data Sheet, Rev. 1.07
136
Freescale Semiconductor