MC9S12E128CFUE Datasheet, PDF (330/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.3.2 Register Descriptions
The address of a register is the sum of a base address and an address offset. The base address is defined at
the chip level and the address offset is defined at the module level.
11.3.2.1 PMF Configure 0 Register (PMFCFG0)
Module Base + 0x0000
7
R
WP
W
Reset
0
6
MTG
5
EDGEC
4
EDGEB
3
EDGEA
2
INDEPC
0
0
0
0
0
Figure 11-4. PMF Configure 0 Register (PMFCFG0)
Read anytime.
See bit description for write conditions.
1
INDEPB
0
0
INDEPA
0
Table 11-2. PMFCFG0 Field Descriptions
Field
7
WP
6
MTG
5
EDGEC
4
EDGEB
Description
Write Protect — This bit enables write protection to be used for all write-protectable registers. While clear, WP
allows write-protected registers to be written. When set, WP prevents any further writes to write-protected
registers. Once set, WP can be cleared only by reset.
0 Write-protectable registers may be written.
1 Write-protectable registers are write-protected.
Multiple Timebase Generators — This bit determines the number of timebase counters used. Once set, MTG
can be cleared only by reset.
If MTG is set, PWM generators B and C and registers $xx28–$xx37 are available. The three generators have
their own variable frequencies and are not synchronized.
If MTG is cleared, PMF registers from $xx28–$xx37 can not be written and read zeroes, and bits EDGEC and
EDGEB are ignored. Pair A, Pair B and Pair C PWMs are synchronized to PWM generator A and use registers
from $xx20–$xx27.
0 Single timebase generator.
1 Multiple timebase generators.
Edge-Aligned or Center-Aligned PWM for Pair C — This bit determines whether PWM4 and PWM5 channels
will use edge-aligned or center-aligned waveforms. This bit has no effect if MTG bit is cleared. This bit cannot be
modified after the WP bit is set.
0 PWM4 and PWM5 are center-aligned PWMs
1 PWM4 and PWM5 are edge-aligned PWMs
Edge-Aligned or Center-Aligned PWM for Pair B — This bit determines whether PWM2 and PWM3 channels
will use edge-aligned or center-aligned waveforms. This bit has no effect if MTG bit is cleared. This bit cannot be
modified after the WP bit is set.
0 PWM2 and PWM3 are center-aligned PWMs
1 PWM2 and PWM3 are edge-aligned PWMs
MC9S12E128 Data Sheet, Rev. 1.07
330
Freescale Semiconductor