MC9S12E128CFUE Datasheet, PDF (376/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
LDFQ[3:0] = 00 = Reload every cycle
Up-Only
COUNTER
LDOK = 1
1
MODULUS = 3
4
PWM VALUE = 2
2
PWMRF = 1
1
1
0
2
1
2
2
1
1
PWM
Figure 11-73. Untitled Figure
11.4.7.4 Initialization
Initialize all registers and set the LDOK bit before setting the PWMEN bit. With LDOK set, setting
PWMEN for the first time after reset, immediately loads the PWM generator thereby setting the PWMRF
flag. PWMRF generates a CPU interrupt request if the PWMRIE bit is set. In complementary channel
operation with current-status correction selected, PWM value registers one, three, and five control the
outputs for the first PWM cycle.
NOTE
Even if LDOK is not set, setting PWMEN also sets the PWMRF flag. To
prevent a CPU interrupt request, clear the PWMRIE bit before setting
PWMEN.
Setting PWMEN for the first time after reset without first setting LDOK loads a prescaler divisor of one,
a PWM value of $0000, and an unknown modulus. The PWM generator uses the last values loaded if
PWMEN is cleared and then set while LDOK equals zero.Initializing the deadtime register, after setting
PWMEN or OUTCTLx, can cause an improper deadtime insertion. However, the deadtime can never be
shorter than the specified value.
IPBus
CLOCK
PWMEN
BIT
PWM
HI-Z
PINS
HI-Z
ACTIVE
Figure 11-74. PWMEN and PWM Pins in Independent Operation
IPBus
CLOCK
PWMEN
BIT
PWM
PINS
HI-Z
HI-Z
ACTIVE
Figure 11-75. PWMEN and PWM Pins in Complementary Operation
MC9S12E128 Data Sheet, Rev. 1.07
376
Freescale Semiconductor