MC9S12E128CFUE Datasheet, PDF (519/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

18.3.2 Register Descriptions
Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.3.2.1 Port A Data Register (PORTA)
7
6
5
4
3
2
1
R
Bit 7
6
5
4
3
2
1
W
Reset
0
0
0
0
0
0
0
Single Chip PA7
PA6
PA5
PA4
PA3
PA2
PA1
Expanded Wide,
Emulation Narrow with AB/DB15
IVIS, and Peripheral
AB/DB14
AB/DB13
AB/DB12
AB/DB11
AB/DB10
AB/DB9
Expanded Narrow AB15 and AB14 and AB13 and AB12 and AB11 and AB10 and AB9 and
DB15/DB7 DB14/DB6 DB13/DB5 DB12/DB4 DB11/DB3 DB10/DB2 DB9/DB1
Figure 18-2. Port A Data Register (PORTA)
0
Bit 0
0
PA0
AB/DB8
AB8 and
DB8/DB0
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines
D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in
single-chip mode, these pins can be used as general-purpose I/O. Data direction register A (DDRA)
determines the primary direction of each pin. DDRA also determines the source of data for a read of
PORTA.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
NOTE
To ensure that you read the value present on the PORTA pins, always wait
at least one cycle after writing to the DDRA register before reading from the
PORTA register.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
519