MC9S12E128CFUE Datasheet, PDF (146/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 3 Port Integration Module (PIM9E128V1)
3.3.4.3 Port Q Data Direction Register (DDRQ)
7
R
0
W
6
DDRQ6
5
DDRQ5
4
DDRQ4
3
DDRQ3
2
DDRQ2
1
DDRQ1
0
DDRQ0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 3-25. Port Q Data Direction Register (DDRQ)
Read: Anytime. Write: Anytime.
This register configures port pins PQ[6:0] as either input or output.
If a PMF function is enabled, the corresponding pin is forced to be an input and the associated Data
Direction Register bit has no effect. If a PMF channel is disabled, the corresponding Data Direction
Register bit reverts to control the I/O direction of the associated pin.
Table 3-18. DDRQ Field Descriptions
Field
6:0
Data Direction Port Q
DDRQ[6:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
3.3.4.4 Port Q Reduced Drive Register (RDRQ)
7
R
0
W
6
RDRQ6
5
RDRQ5
4
RDRQ4
3
RDRQ3
2
RDRQ2
1
RDRQ1
0
RDRQ0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 3-26. Port Q Reduced Drive Register (RDRQ)
Read:Anytime. Write:Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 3-19. RDRQ Field Descriptions
Field
Description
6:0
Reduced Drive Port Q
RDRQ[6:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12E128 Data Sheet, Rev. 1.07
146
Freescale Semiconductor