MC9S12E128CFUE Datasheet, PDF (586/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Appendix A Electrical Characteristics
In Figure A-5 the timing diagram for master mode with transmission format CPHA=1 is depicted.
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN²
9
MOSI
(OUTPUT)
PORT DATA
MASTER MSB OUT²
12
12
BIT 6 . . . 1
11
BIT 6 . . . 1
13
3
13
LSB IN
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-5. SPI Master Timing (CPHA=1)
In Table A-17 the timing characteristics for master mode are listed.
Table A-17. SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
C
Characteristic
P SCK Frequency
P SCK Period
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Data Valid after SCK Edge
D Data Valid after SS fall (CPHA = 0)
D Data Hold Time (Outputs)
D Rise and Fall Time Inputs
D Rise and Fall Time Outputs
Symbol
Min
Typ
f_sck
1/2048
—
t_sck
2
—
t_lead
—
1/2
t_lag
—
1/2
t_wsck
—
1/2
t_su
8
—
t_hi
8
—
t_vsck
—
—
t_vss
—
—
t_ho
20
—
t_rfi
—
—
t_rfo
—
—
Max
1/2
2048
—
—
—
—
—
30
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
MC9S12E128 Data Sheet, Rev. 1.07
586
Freescale Semiconductor