MC9S12E128CFUE Datasheet, PDF (366/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.4.5.2 Manual Correction
The IPOLx bits select either the odd or the even PWM value registers to use in the next PWM cycle.
Bit
IPOLA
IPOLB
IPOLC
Table 11-48. Top/Bottom Manual Correction
Logic Atate
0
1
0
1
0
1
Output Control
PMFVAL0 controls PWM0/PWM1 pair
PMFVAL1 controls PWM0/PWM1 pair
PMFVAL2 controls PWM2/PWM3 pair
PMFVAL3 controls PWM2/PWM3 pair
PMFVAL4 controls PWM4/PWM5 pair
PMFVAL5 controls PWM4/PWM5 pair
NOTE
IPOLx bits are buffered so only one PWM register is used per PWM cycle.
If an IPOLx bit changes during a PWM period, the new value does not take
effect until the next PWM period.
IPOLx bits take effect at the end of each PWM cycle regardless of the state
of the load okay bit, LDOK.
PWM CONTROLLED BY
ODD PWMVALREGISTER
PWM CONTROLLED BY EVEN
PWMVAL REGISTER
A
B
A/B
DEADTIME
GENERATOR
IPOLx BIT
PWM CYCLE START
D
Q
CLK
TOP PWM
BOTTOM PWM
Figure 11-54. Internal Correction Logic when ISENS = 01
To detect the current status, the voltage on each ISx pin is sampled twice in a PWM period, at the end of
each deadtime. The value is stored in the DTx bits in the PMF Deadtime Sample register (PMFDTMS).
The DTx bits are a timing marker especially indicating when to toggle between PWM value registers.
Software can then set the IPOLx bit to toggle PMFVAL registers according to DTx values.
MC9S12E128 Data Sheet, Rev. 1.07
366
Freescale Semiconductor