MC9S12E128CFUE Datasheet, PDF (324/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.1.2 Modes of Operation
Care must be exercised when using this module in the modes listed in Table 11-1. PWM outputs are placed
in their inactive states in stop mode, and optionally under WAIT and freeze modes. PWM outputs will be
reactivated (assuming they were active to begin with) when these modes are exited.
Mode
Stop
Wait
Freeze
Table 11-1. Modes When PWM Operation is Restricted
Description
PWM outputs are disabled
PWM outputs are disabled as a function of the PMFWAI bit.
PWM outputs are disabled as a function of the PMFFRZ bit.
11.1.3 Block Diagrams
Figure 11-1 provides an overview of the PMF module.
The Mux/Swap/Current Sense block is tightly integrated with the dead time insertion block . This detail
is shown in Figure 11-2.
NOTE
It is possible to have both channels of a complementary pair to be high. For
example, if the TOPNEGA (negative polarity for PWM0), BOTNEGA
(negative polarity for PWM1), MASK0, and MASK1 bits are set, both the
PWM complementary outputs of generator A will be high. See
Section 11.3.2.2, “PMF Configure 1 Register (PMFCFG1)” for the
description of TOPNEG and BOTNEG bits, and Section 11.3.2.3, “PMF
Configure 2 Register (PMFCFG2)” for the description of the MSK0 and
MSK1 bits.
MC9S12E128 Data Sheet, Rev. 1.07
324
Freescale Semiconductor