MC9S12E128CFUE Datasheet, PDF(71/606 Page) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

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MC9S12E128CFUE Datasheet, PDF (71/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

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Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)

1.4.37 PS0 / RXD0 â Port S I/O Pin 0

PS0 is a general purpose input or output. When the Serial Communications Interface 0 (SCI0) receiver is

enabled the PS0 pin is conï¬gured as the receive pin RXD0 of SCI0. While in reset and immediately out of

reset the PS0 pin is conï¬gured as a high impedance input pin. Consult the Port Integration Module (PIM)

PIM_9E128 block description chapter and the SCI block description chapter for information about pin

conï¬gurations.

1.4.38 PT[7:4] / IOC1[7:4]â Port T I/O Pins [7:4]

PT[7:4] are general purpose input or output pins. When the Timer system 1 (TIM1) is enabled they can

also be conï¬gured as the TIM1 input capture or output compare pins IOC1[7-4]. While in reset and

immediately out of reset the PT[7:4] pins are conï¬gured as a high impedance input pins. Consult the Port

Integration Module (PIM) PIM_9E128 block description chapter and the TIM_16B4C block description

chapter for information about pin conï¬gurations.

1.4.39 PT[3:0] / IOC0[7:4]â Port T I/O Pins [3:0]

PT[3:0] are general purpose input or output pins. When the Timer system 0 (TIM0) is enabled they can

also be conï¬gured as the TIM0 input capture or output compare pins IOC0[7-4]. While in reset and

immediately out of reset the PT[3:0] pins are conï¬gured as a high impedance input pins. Consult the Port

Integration Module (PIM) PIM_9E128 block description chapter and the TIM_16B4C block description

chapter for information about pin conï¬gurations.

1.4.40 PU[7:6] â Port U I/O Pins [7:6]

PU[7:6] are general purpose input or output pins. While in reset and immediately out of reset the PU[7:6]

pins are conï¬gured as a high impedance input pins. Consult the Port Integration Module (PIM)

PIM_9E128 for information about pin conï¬gurations. PU[7:6] are not available in the 80 pin package

version.

1.4.41 PU[5:4] / PW1[5:4] â Port U I/O Pins [5:4]

PU[5:4] are general purpose input or output pins. When the Pulse Width Modulator (PWM) is enabled the

PU[5:4] output pins, individually or as a pair, can be conï¬gured as PW1[5:4] outputs. While in reset and

immediately out of reset the PU[5:4] pins are conï¬gured as a high impedance input pins. Consult the Port

Integration Module (PIM) PIM_9E128 block description chapter and the PWM_8B6C block description

chapter for information about pin conï¬gurations. PU[5:4] are not available in the 80 pin package version.

1.4.42 PU[3:0] / IOC2[7:4]/PW1[3:0] â Port U I/O Pins [3:0]

PU[3:0] are general purpose input or output pins. When the Timer system 2 (TIM2) is enabled they can

also be conï¬gured as the TIM2 input capture or output compare pins IOC2[7-4]. When the Pulse Width

Modulator (PWM) is enabled the PU[3:0] output pins, individually or as a pair, can be conï¬gured as

PW1[3:0] outputs. The MODRR register in the Port Integration Module determines if the TIM2 or PWM

function is selected. While in reset and immediately out of reset the PU[3:0] pins are conï¬gured as a high

MC9S12E128 Data Sheet, Rev. 1.07

Freescale Semiconductor

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