|
MC9S12E128CFUE Datasheet, PDF (475/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet | |||
|
◁ |
Chapter 16 Debug Module (DBGV1)
â Data associated with event B trigger modes
â Detail report mode stores address and data for all cycles except program (P) and free (f) cycles
â Current instruction address when in proï¬ling mode
â BGND is not considered a change-of-ï¬ow (cof) by the debugger
16.1.2 Modes of Operation
There are two main modes of operation: breakpoint mode and debug mode. Each one is mutually exclusive
of the other and selected via a software programmable control bit.
In the breakpoint mode there are two sub-modes of operation:
⢠Dual address mode, where a match on either of two addresses will cause the system to enter
background debug mode (BDM) or initiate a software interrupt (SWI).
⢠Full breakpoint mode, where a match on address and data will cause the system to enter
background debug mode (BDM) or initiate a software interrupt (SWI).
In debug mode, there are several sub-modes of operation.
⢠Trigger modes
There are many ways to create a logical trigger. The trigger can be used to capture bus information
either starting from the trigger or ending at the trigger. Types of triggers (A and B are registers):
â A only
â A or B
â A then B
â Event only B (data capture)
â A then event only B (data capture)
â A and B, full mode
â A and not B, full mode
â Inside range
â Outside range
⢠Capture modes
There are several capture modes. These determine which bus information is saved and which is
ignored.
â Normal: save change-of-ï¬ow program fetches
â Loop1: save change-of-ï¬ow program fetches, ignoring duplicates
â Detail: save all bus operations except program and free cycles
â Proï¬le: poll target from external device
16.1.3 Block Diagram
Figure 16-1 is a block diagram of this module in breakpoint mode. Figure 16-2 is a block diagram of this
module in debug mode.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
475
|
▷ |