MC9S12E128CFUE Datasheet, PDF (518/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.3 Memory Map and Register Definition
A summary of the registers associated with the MEBI sub-block is shown in Table 18-2. Detailed
descriptions of the registers and bits are given in the subsections that follow. On most chips the registers
are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions.
18.3.1 Module Memory Map
Table 18-2. MEBI Memory Map
Address
Offset
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x001E
0x00032
0x00033
Use
Port A Data Register (PORTA)
Port B Data Register (PORTB)
Data Direction Register A (DDRA)
Data Direction Register B (DDRB)
Reserved
Reserved
Reserved
Reserved
Port E Data Register (PORTE)
Data Direction Register E (DDRE)
Port E Assignment Register (PEAR)
Mode Register (MODE)
Pull Control Register (PUCR)
Reduced Drive Register (RDRIV)
External Bus Interface Control Register (EBICTL)
Reserved
IRQ Control Register (IRQCR)
Port K Data Register (PORTK)
Data Direction Register K (DDRK)
Access
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
MC9S12E128 Data Sheet, Rev. 1.07
518
Freescale Semiconductor