MC9S12E128CFUE Datasheet, PDF (129/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 3 Port Integration Module (PIM9E128V1)
Refer to the ATD block description chapter for information on the ATDDIEN0 and ATDDIEN1 registers.
During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is
disabled).
3.3.1.1 Port AD I/O Register (PTAD)
7
R
PTAD15
W
KWU: KWAD15
ATD: AN15
Reset
0
6
PTAD14
KWAD14
AN14
0
5
PTAD13
KWAD13
AN13
0
4
PTAD12
KWA12
AN12
0
3
PTAD11
2
PTAD10
KWAD11
AN11
0
KWAD10
AN10
0
1
PTAD9
KWAD9
AN9
0
0
PTAD8
KWAD8
AN8
0
R
W
KWU:
ATD:
Reset
7
PTAD7
KWAD7
AN7
0
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
KWAD6
AN6
0
KWAD5
KWAD4
KWAD3
KWAD2
AN5
AN4
AN3
AN2
0
0
0
0
Figure 3-2. Port AD I/O Register (PTAD)
1
PTAD1
KWAD1
AN1
0
0
PTAD0
KWAD0
AN0
0
Read: Anytime. Write: Anytime.
If the data direction bit of the associated I/O pin (DDRADx) is set to 1 (output), a write to the
corresponding I/O Register bit sets the value to be driven to the Port AD pin. If the data direction bit of the
associated I/O pin (DDRADx) is set to 0 (input), a write to the corresponding I/O Register bit takes place
but has no effect on the Port AD pin.
If the associated data direction bit (DDRADx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN0(1) bit is
set to 0 (digital input buffer is disabled), the associated I/O register bit (PTADx) reads “1”.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN0(1) bit is
set to 1 (digital input buffer is enabled), a read returns the value of the pin.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
129