MC9S12E128CFUE Datasheet, PDF (391/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

PCKB2
0
0
0
0
1
1
1
1
Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
Table 12-6. Clock B Prescaler Selects
PCKB1
0
0
1
1
0
0
1
1
PCKB0
0
1
0
1
0
1
0
1
Value of Clock B
Bus Clock
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 128
PCKA2
0
0
0
0
1
1
1
1
Table 12-7. Clock A Prescaler Selects
PCKA1
0
0
1
1
0
0
1
1
PCKA0
0
1
0
1
0
1
0
1
Value of Clock A
Bus Clock
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 128
12.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains six control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center
aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference
Section 12.4.2.5, “Left Aligned Outputs,” and Section 12.4.2.6, “Center Aligned Outputs,” for a more
detailed description of the PWM output modes.
7
R
0
W
6
5
4
3
2
1
0
CAE5
CAE4
CAE3
CAE2
CAE1
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-7. PWM Center Align Enable Register (PWMCAE)
Read: anytime
Write: anytime
NOTE
Write these bits only when the corresponding channel is disabled.
0
CAE0
0
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
391