MC9S12E128CFUE Datasheet, PDF (119/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 3
Port Integration Module (PIM9E128V1)
3.1 lntroduction
The port integration module establishes the interface between the peripheral modules and the I/O pins for
for ports AD, M, P, Q, S, T and U.
This section covers:
• Port A, B, E, and K and the BKGD pin
• Port AD associated with ATD module (channels 15 through 0) and keyboard wake-up interrupts
• Port M connected to 2 DAC, 1 IIC and 1 SCI (SCI2) modules
• Port P and port Q connected to PMF module
• Port S connected to 2 SCI (SCI0 and SCI1) and 1 SPI modules
• Port T connected to 2 TIM (TIM0 and TIM1) modules
• Port U connected to 1 TIM (TIM2) and 1 PWM modules
Each I/O pin can be configured by several registers: input/output selection, drive strength reduction,
enable and select of pull resistors, wired-or mode selection, interrupt enable, and/or status flags.
NOTE
Refer to the MEBI block description chapter for details on p orts A, B, E and
K, and the BKGD pin.
3.1.1 Features
A standard port has the following minimum features:
• Input/output selection
• 5-V output drive with two selectable drive strength (or slew rates)
• 5-V digital and analog input
• Input with selectable pull-up or pull-down device
Optional features:
• Open drain for wired-OR connections
• Interrupt input with glitch filtering
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
119