MC9S12E128CFUE Datasheet, PDF (520/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.3.2.2 Port B Data Register (PORTB)
7
6
5
4
3
2
R
Bit 7
6
5
4
3
2
W
Reset
0
0
0
0
0
0
Single Chip PB7
PB6
PB5
PB4
PB3
PB2
Expanded Wide,
Emulation Narrow with AB/DB7
IVIS, and Peripheral
AB/DB6
AB/DB5
AB/DB4
AB/DB3
AB/DB2
Expanded Narrow AB7
AB6
AB5
AB4
AB3
AB2
Figure 18-3. Port A Data Register (PORTB)
1
1
0
PB1
AB/DB1
AB1
0
Bit 0
0
PB0
AB/DB0
AB0
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7
through D0 respectively. When this port is not used for external addresses, such as in single-chip mode,
these pins can be used as general-purpose I/O. Data direction register B (DDRB) determines the primary
direction of each pin. DDRB also determines the source of data for a read of PORTB.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
NOTE
To ensure that you read the value present on the PORTB pins, always wait
at least one cycle after writing to the DDRB register before reading from the
PORTB register.
MC9S12E128 Data Sheet, Rev. 1.07
520
Freescale Semiconductor