MC9S12E128CFUE Datasheet, PDF (81/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
1.10 Recommended Printed Circuit Board Layout
The Printed Circuit Board (PCB) must be carefully laid out to ensure proper operation of the voltage
regulator as well as the MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1–C6).
• Central point of the ground star should be the VSSR pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
• VSSPLL must be directly connected to VSSR.
• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
Table 1-11. Recommended Decoupling Capacitor Choice
Component
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
R1
Q1
Purpose
VDD1 filter cap
VDD2 filter cap (80 QFP only)
VDDA filter cap
VDDR filter cap
VDDPLL filter cap
VDDX filter cap
OSC load cap
OSC load cap
PLL loop filter cap
PLL loop filter cap
DC cutoff cap
PLL loop filter res
Quartz
Type
Ceramic X7R
Ceramic X7R
Ceramic X7R
X7R/tantalum
Ceramic X7R
X7R/tantalum
Value
100–220nF
100–220nF
100nF
>=100nF
100nF
>=100nF
See PLL specification chapter
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
81