MC9S12E128CFUE Datasheet, PDF (151/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

3.3.5.6
Port S Polarity Select Register (PPSS)
Chapter 3 Port Integration Module (PIM9E128V1)
R
W
Reset
7
PPSS7
0
6
PPSS6
5
PPSS5
4
PPSS4
3
PPSS3
2
PPSS2
0
0
0
0
0
Figure 3-34. Port S Polarity Select Register (PPSS)
1
PPSS1
0
0
PPSS0
0
Read: Anytime. Write: Anytime.
The Port S Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin.
The Port S Polarity Select Register is effective only when the corresponding Data Direction Register bit
is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 3-25. PPSS Field Descriptions
Field
Description
7:0
Pull Select Port S
PPSS[7:0] 0 A pull-up device is connected to the associated port S pin.
1 A pull-down device is connected to the associated port S pin.
3.3.5.7 Port S Wired-OR Mode Register (WOMS)
7
R
WOMS7
W
6
WOMS6
5
WOMS5
4
WOMS4
3
WOMS3
2
WOMS2
1
WOMS1
0
WOMS0
Reset
0
0
0
0
0
0
0
0
Figure 3-35. Port S Wired-OR Mode Register (WOMS)
Read: Anytime. Write: Anytime.
This register selects whether a port S output is configured as push-pull or wired-or. When a Wired-OR
Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a
high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured
as an input.
Table 3-26. WOMS Field Descriptions
Field
Description
7:0
Wired-OR Mode Port S
WOMS[7:0] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
151