MC9S12E128CFUE Datasheet, PDF (535/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.3.2.16 Port K Data Direction Register (DDRK)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 18-20. Port K Data Direction Register (DDRK)
Read: Anytime
Write: Anytime
This register determines the primary direction for each port K pin configured as general-purpose I/O. This
register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is
set. Therefore, these accesses will be echoed externally.
Table 18-14. EBICTL Field Descriptions
Field
7:0
DDRK
Description
Data Direction Port K Bits
0 Associated pin is a high-impedance input
1 Associated pin is an output
Note: It is unwise to write PORTK and DDRK as a word access. If you are changing port K pins from inputs to
outputs, the data may have extra transitions during the write. It is best to initialize PORTK before enabling
as outputs.
Note: To ensure that you read the correct value from the PORTK pins, always wait at least one cycle after writing
to the DDRK register before reading from the PORTK register.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
535