MC9S12E128CFUE Datasheet, PDF (152/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

Chapter 3 Port Integration Module (PIM9E128V1)
3.3.6 Port T
Port T is associated with two 4-channel timers (TIM0 and TIM1). Each pin is assigned to these modules
according to the following priority: TIM1/TIM0 > general-purpose I/O.
If the timer TIM0 is enabled, the channels configured for output compare are available on port T pins
PT[3:0]. If the timer TIM1 is enabled, the channels configured for output compare are available on port T
pins PT[7:4].
Refer to the TIM block description chapter for information on enabling and disabling the TIM module.
During reset, port T pins are configured as high-impedance inputs.
3.3.6.1 Port T I/O Register (PTT)
R
W
TIM:
7
PTT7
OC17
6
PTT6
OC16
5
PTT5
OC15
4
PTT4
OC14
3
PTT3
OC07
2
PTT2
OC06
1
PTT1
OC05
0
PTT0
OC04
Reset
0
0
0
0
0
0
0
0
Figure 3-36. Port T I/O Register (PTT)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRTx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRTx) is set to 0 (input), a read returns the value of the pin.
3.3.6.2 Port T Input Register (PTIT)
7
R PTIT7
W
6
PTIT6
5
PTIT5
4
PTIT4
3
PTIT3
2
PTIT2
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 3-37. Port T Input Register (PTIT)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIT1
u
0
PTIT0
u
MC9S12E128 Data Sheet, Rev. 1.07
152
Freescale Semiconductor