MC9S12E128CFUE Datasheet, PDF (143/606 Pages) Freescale Semiconductor, Inc – MC9S12E128 Data Sheet

3.3.3.3
Port P Data Direction Register (DDRP)
Chapter 3 Port Integration Module (PIM9E128V1)
7
R
0
W
6
5
4
3
2
1
0
0
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 3-19. Port P Data Direction Register (DDRP)
Read: Anytime. Write: Anytime.
This register configures port pins PP[5:0] as either input or output.
If a PMF channel is enabled, the corresponding pin is forced to be an output and the associated Data
Direction Register bit has no effect. If a PMF channel is disabled, the corresponding Data Direction
Register bit reverts to control the I/O direction of the associated pin.
Table 3-14. DDRP Field Descriptions
Field
5:0
Data Direction Port P
DDRP[5:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
3.3.3.4 Port P Reduced Drive Register (RDRP)
7
R
0
W
6
5
4
3
2
1
0
0
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 3-20. Port P Reduced Drive Register (RDRP)
Read:Anytime. Write:Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 3-15. RDRP Field Descriptions
Field
Description
5:0
Reduced Drive Port P
RDRP[5:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
143