MC68HC908GP32_08 Datasheet, PDF (87/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

COP Control Register
7.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See
Chapter 6 Configuration Register (CONFIG).)
7.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register.
(See Chapter 6 Configuration Register (CONFIG).)
7.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 7-2. COP Control Register (COPCTL)
7.5 Interrupts
The COP does not generate CPU interrupt requests.
7.6 Monitor Mode
When monitor mode is entered with V_TST on the IRQ pin, the COP is disabled as long as V_TST remains
on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having V_TST on the IRQ pin, the COP is automatically disabled until a POR occurs.
7.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear
the COP counter in a CPU interrupt routine.
7.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
87