MC68HC908GP32_08 Datasheet, PDF (225/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Monitor Module (MON)
Table 18-1. Monitor Mode Signal Requirements and Options
Mode
Serial
IRQ
RST
Reset
Vector
Communication
Mode
Selection
Divider
PLL
PTA0 PTA7 PTC0 PTC1 PTC3
COP
Communication
Speed
External Bus
Baud
Clock Frequency Rate
V_DD
V_TST or
X
1
Normal
V_TST
Monitor
V_DD
V_TST or
X
1
V_TST
0
1
0
0
OFF Disabled
4.9152
MHz
2.457 MHz
9600
0
1
0
1
OFF Disabled
9.8304
MHz
2.457 MHz
9600
Forced
V_DD
V_DD
$FFFF
(blank)
1
Monitor
V_SS
V_DD
$FFFF
(blank)
1
0
X
X
X
OFF Disabled
9.8304
MHz
2.457 MHz
9600
0
X
X
X
ON Disabled
32.768
kHz
2.457 MHz
9600
V_DD V_{DD Not}
User or or $FFFF X
V_SS V_TST
X
X
X
X
X Enabled X
X
X
MON08
Function
[Pin No.]
V_TST
[6]
RST
[4]
—
COM
[8]
SSEL MOD0 MOD1 DIV4
[10] [12] [14] [16]
—
—
OSC1
[13]
—
—
1. PTA0 must have a pullup resistor to V_DD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus
frequency / 256.
3. External clock is a 4.9152 MHz or 9.8304 MHz canned oscillator on OSC1 or a 32.768 kHz crystal on OSC1 and OSC2.
4. X = don’t care
5. MON08 pin refers to P&E Microcomputer Systems’ MON08-Cyclone 2 by 8-pin connector.
NC
1
NC
3
NC
5
NC
7
NC
9
NC 11
OSC1 13
V_DD
15
2
GND
4
RST
6
IRQ
8
PTA0
10
PTA7
12
PTC0
14
PTC1
16
PTC3
18.3.1.1 Normal Monitor Mode
When V_TST is applied to IRQ and PTC3 is low upon monitor mode entry, the bus frequency is a
divide-by-two of the input clock. If PTC3 is high with V_TST applied to IRQ upon monitor mode entry, the
bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when entering monitor
mode causes a bypass of a divide-by-two stage at the oscillator only if V_TST is applied to IRQ. In this
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
225