MC68HC908GP32_08 Datasheet, PDF (158/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 14-1. SIM Block Diagram
INTERRUPT SOURCES
CPU INTERFACE
Addr. Register Name
$FE00
Read:
SIM Break Status Register
(SBSR)
Write:
Reset:
Note: Writing a logic 0 clears SBSW.
$FE01
Read:
SIM Reset Status Register
(SRSR)
Write:
POR:
$FE02
Read:
SIM Upper Byte Address
Register (SUBAR)
Write:
Reset:
Bit 7
R
POR
1
R
6
5
R
R
PIN
COP
0
0
R
R
= Unimplemented
4
3
2
1
SBSW
R
R
R
Note
0
ILOP
ILAD MODRST LVI
0
0
0
0
R
R
R
R
R = Reserved
Figure 14-2. SIM I/O Register Summary
Bit 0
R
0
0
R
MC68HC908GP32 Data Sheet, Rev. 10
158
Freescale Semiconductor