MC68HC908GP32_08 Datasheet, PDF (71/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

5.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL)
(See 5.5.1 PLL Control Register.)
• PLL bandwidth control register (PBWC)
(See 5.5.2 PLL Bandwidth Control Register.)
• PLL multiplier select register high (PMSH)
(See 5.5.3 PLL Multiplier Select Register High.)
• PLL multiplier select register low (PMSL)
(See 5.5.4 PLL Multiplier Select Register Low.)
• PLL VCO range select register (PMRS)
(See 5.5.5 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 5.5.6 PLL Reference Divider Select Register.)
Figure 5-3 is a summary of the CGM registers.
CGM Registers
Addr. Register Name
Bit 7
6
5
$0036
Read:
PLL Control Register
(PCTL)
Write:
Reset:
PLLIE
0
PLLF
PLLON
0
1
$0037
PLL Bandwidth Control ^Read:
Register Write:
AUTO
LOCK
ACQ
(PBWC) Reset: 0
0
0
PLL Multiplier Select High ^{Read: 0}
0
0
$0038
Register Write:
(PMSH) Reset: 0
0
0
$0039
PLL Multiplier Select Low ^Read:
Register Write:
MUL7
MUL6
MUL5
(PMSL) Reset: 0
1
0
$003A
PLL VCO Range Select ^Read:
Register Write:
VRS7
VRS6
VRS5
(PMRS) Reset: 0
1
0
PLL Reference Divider ^{Read: 0}
0
0
$003B
Select Register Write:
(PMDS) Reset: 0
0
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
4
3
2
BCS
PRE1
PRE0
0
0
0
0
0
0
0
0
0
MUL4
0
VRS4
0
0
0
R
0
MUL11
0
MUL3
0
VRS3
0
RDS3
0
= Reserved
0
MUL10
0
MUL2
0
VRS2
0
RDS2
0
Figure 5-3. CGM I/O Register Summary
1
VPR1
0
0
0
MUL9
0
MUL1
0
VRS1
0
RDS1
0
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
71