MC68HC908GP32_08 Datasheet, PDF (58/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Analog-to-Digital Converter (ADC)
4.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 4-3. ADC Data Register (ADR)
4.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
ADIV2 ADIV1 ADIV0 ADICLK
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 4-4. ADC Clock Register (ADCLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock. Table 4-2 shows the available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Table 4-2. ADC Clock Divide Ratio
ADIV2
ADIV1
0
0
0
0
0
1
0
1
1
X
X = don’t care
ADIV0
0
1
0
1
X
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
MC68HC908GP32 Data Sheet, Rev. 10
58
Freescale Semiconductor