MC68HC908GP32_08 Datasheet, PDF (73/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

CGM Registers
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
5.3.8 Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) PRE1 and PRE0 cannot be written when the
PLLON bit is set. Reset clears these bits.
NOTE
The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
Table 5-2. PRE1 and PRE0 Programming
PRE1 and PRE0
00
01
10
11
P
Prescaler Multiplier
0
1
1
2
2
4
3
8
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See 5.3.3 PLL Circuits, 5.3.6 Programming the PLL, and 5.5.5 PLL VCO Range Select
Register.) controls the hardware center-of-range frequency, f_VRS. VPR1:VPR0 cannot be written when
the PLLON bit is set. Reset clears these bits.
Table 5-3. VPR1 and VPR0 Programming
VPR1 and VPR0
00
01
10
11
E
VCO Power-of-Two
Range Multiplier
0
1
1
2
2
4
3⁽¹⁾
8
1. Do not program E to a value of 3.
5.5.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
73