MC68HC908GP32_08 Datasheet, PDF (102/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

External Interrupt (IRQ)
Interrupt signals on the IRQ pin are latched into the IRQ latch. The IRQ latch remains set until one of the
following actions occurs:
• IRQ vector fetch. An IRQ vector fetch automatically generates an interrupt acknowledge signal that
clears the latch that caused the vector fetch.
• Software clear. Software can clear the IRQ latch by writing a 1 to ACK in the interrupt status and
control register (INTSCR).
• Reset. A reset automatically clears the IRQ latch.
The external IRQ pin is falling edge sensitive out of reset and is software-configurable to be either falling
edge or falling edge and low level sensitive. MODE in INTSCR controls the triggering sensitivity of the
IRQ pin.
ACK is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. A trigger
event (falling edge or low level) that occurs after writing to ACK latches another interrupt request.
IRQF in INTSCR can be read to check for pending interrupts. IRQF is not affected by IMASK, which
makes it useful in applications where polling is preferred.
When set, IMASK in INTSCR masks the IRQ interrupt request.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including the IRQ interrupt request.
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. An IRQ vector fetch,
software clear, or reset clears the IRQ latch.
9.3.1 MODE = 1
If MODE is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set, both of
the following actions must occur to clear the IRQ interrupt request:
• Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active.
• IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signal
to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK
in INTSCR.
The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order.
The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false IRQ interrupts
by masking interrupt requests in the interrupt routine.
9.3.2 MODE = 0
If MODE is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch or
software clear immediately clears the IRQ latch.
MC68HC908GP32 Data Sheet, Rev. 10
102
Freescale Semiconductor