MC68HC908GP32_08 Datasheet, PDF (168/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
Bit 0 and Bit 1 — Always read 0
Interrupt Status Register 2
Address: $FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read: IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 14-13. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 14-3.
1 = Interrupt request present
0 = No interrupt request present
Interrupt Status Register 3
Address: $FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
IF16
IF15
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 14-14. Interrupt Status Register 3 (INT3)
Bits 7–2 — Always read 0
IF16–IF15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the source shown in Table 14-3.
1 = Interrupt request present
0 = No interrupt request present
14.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
14.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting
its break interrupt output. (See Chapter 17 Timer Interface Module (TIM).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module
to see how each module is affected by the break state.
MC68HC908GP32 Data Sheet, Rev. 10
168
Freescale Semiconductor