MC68HC908GP32_08 Datasheet, PDF (215/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Chapter 18
Development Support
18.1 Introduction
This section describes the break module, the monitor module (MON), and the monitor mode entry
methods.
18.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features of the break module include:
• Accessible input/output (I/O) registers during the break Interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break interrupts
18.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
Figure 18-1 shows the structure of the break module.
Figure 18-2 provides a summary of the I/O registers.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
215