MC68HC908GP32_08 Datasheet, PDF (119/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
V_DD
DDRAx
PTAx
PTAPUEx
READ PTA ($0000)
INTERNAL
PULLUP
DEVICE
Port A
PTAx
Figure 12-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port A pins.
Table 12-2. Port A Pin Functions
PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode
1
0
X⁽¹⁾
Input, V_DD(4)
0
0
X
Input, Hi-Z⁽²⁾
X
1
X
Output
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V_DD by internal pullup device
Accesses to DDRA
Read/Write
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
Accesses to PTA
Read
Write
Pin
PTA7–PTA0⁽³⁾
Pin
PTA7–PTA0⁽³⁾
PTA7–PTA0
PTA7–PTA0
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the eight port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTAPUE7 PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
119