MC68HC908GP32_08 Datasheet, PDF (51/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

3.13 Timebase Module (TBM)
Timebase Module (TBM)
3.13.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before enabling the WAIT instruction.
3.13.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the oscillator has been
enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active
during stop mode. In stop mode, the timebase register is not accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the power consumption by stopping
the timebase before enabling the STOP instruction.
3.14 Exiting Wait Mode
These events restart the CPU clock and load the program counter with the reset vector or with an interrupt
vector:
• External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
• External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the
program counter with the contents of locations: $FFFA and $FFFB; IRQ pin.
• Break interrupt — A break interrupt loads the program counter with the contents of $FFFC and
$FFFD.
• Computer operating properly module (COP) reset — A timeout of the COP counter resets the MCU
and loads the program counter with the contents of $FFFE and $FFFF.
• Low-voltage inhibit module (LVI) reset — A power supply voltage below the V_tripf voltage resets the
MCU and loads the program counter with the contents of locations $FFFE and $FFFF.
• Clock generator module (CGM) interrupt — A CPU interrupt request from the phase-locked loop
(PLL) loads the program counter with the contents of $FFF8 and $FFF9.
• Keyboard module (KBI) interrupt — A CPU interrupt request from the KBI module loads the
program counter with the contents of $FFE0 and $FFE1.
• Timer 1 interface module (TIM1) interrupt — A CPU interrupt request from the TIM1 loads the
program counter with the contents of:
– $FFF2 and $FFF3; TIM1 overflow
– $FFF4 and $FFF5; TIM1 channel 1
– $FFF6 and $FFF7; TIM1 channel 0
• Timer 2 interface module (TIM2) interrupt — A CPU interrupt request from the TIM2 loads the
program counter with the contents of:
– $FFEC and $FFED; TIM2 overflow
– $FFEE and $FFEF; TIM2 channel 1
– $FFF0 and $FFF1; TIM2 channel 0
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
51