MC68HC908GP32_08 Datasheet, PDF (103/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Interrupts
9.4 Interrupts
The interrupt flag (IRQF) is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt
mask bit, IMASK, is used to enable or disable IRQ interrupt requests.
9.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
9.5.1 Wait Mode
The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of wait mode.
9.5.2 Stop Mode
The IRQ module remains active in stop mode and provides an asynchronous wakeup. Clearing IMASK
in INTSCR enables IRQ interrupt requests to bring the MCU out of stop mode.
9.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits
during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing
the second step clears the status bit.
9.7 I/O Signals
The IRQ module does not share its pin with any module on this MCU.
9.7.1 IRQ Input Pins (IRQ)
The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup
device.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
103