MC68HC908GP32_08 Datasheet, PDF (107/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Interrupts
10.4.3 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to pull the pin to a high level.
Therefore a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting IMASKK in INTKBSCR.
2. Enable the KBI pins by setting the appropriate KBIEx bits in INTKBIER.
3. Write to ACKK in INTKBSCR to clear any false interrupts.
4. Clear IMASKK.
An interrupt signal on an edge sensitive pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge and level sensitive pin must be acknowledged after a delay that depends on
the external load.
10.5 Interrupts
The following KBI source can generate interrupt requests:
• Keyboard flag (KEYF) — KEYF is set when any enabled KBI pin is asserted based on the KBI
mode. The keyboard interrupt mask bit, IMASKK, is used to enable or disable KBI interrupt
requests.
10.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
The KBI module remains active in wait mode. Clearing IMASKK in INTKBSCR enables keyboard interrupt
requests to bring the MCU out of wait mode.
10.6.2 Stop Mode
The KBI module remains active in stop mode. Clearing IMASKK in INTKBSCR enables keyboard interrupt
requests to bring the MCU out of stop mode.
10.7 KBI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. BCFE in the break flag control register (BFCR) enables software to clear status bits
during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing
the second step clears the status bit.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
107