MC68HC908GP32_08 Datasheet, PDF (128/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Input/Output (I/O) Ports
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 13 Serial Communications Interface Module (SCI).
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is
clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 13 Serial Communications Interface Module (SCI).
12.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a
logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the
output buffer.
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
DDRE1 DDRE0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-18. Data Direction Register E (DDRE)
DDRE1 and DDRE0 — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE1 and DDRE0, configuring all
port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 12-19 shows the port E I/O logic.
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
WRITE PTE ($0008)
DDREx
PTEx
PTEx
READ PTE ($0008)
Figure 12-19. Port E I/O Circuit
MC68HC908GP32 Data Sheet, Rev. 10
128
Freescale Semiconductor