MC68HC908GP32_08 Datasheet, PDF (224/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Development Support
Table 18-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
must be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
1. If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 4.9152 MHz with PTC3 low or 9.8304 MHz with PTC3 high
– IRQ = V_TST
2. If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = V_DD (this can be implemented through the internal IRQ pullup)
3. If $FFFE and $FFFF contain $FF (erased state):
– IRQ = V_SS (PLL is selected using a 32.768 kHz crystal)
Enter monitor mode with the pin configurations shown in Table 18-1 with a power-on-reset. The rising
edge of reset latches monitor mode. Once monitor mode is latched, the levels on the port pins except
PTA0 can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see 18.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
MC68HC908GP32 Data Sheet, Rev. 10
224
Freescale Semiconductor