MC68HC908GP32_08 Datasheet, PDF (75/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

CGM Registers
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
Bit7–Bit4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
5.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MUL7
Write:
MUL6 MUL5 MUL4
MUL3
MUL2
MUL1
MUL0
Reset: 0
1
0
0
0
0
0
0
Figure 5-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See 5.3.3 PLL Circuits and 5.3.6 Programming the PLL.) MUL7–MUL0 cannot
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
5.5.5 PLL VCO Range Select Register
NOTE
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Address: $003A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
VRS7
Write:
VRS6 VRS5 VRS4
VRS3
VRS2
VRS1
VRS0
Reset: 0
1
0
0
0
0
0
0
Figure 5-8. PLL VCO Range Select Register (PMRS)
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (See 5.3.3 PLL Circuits, 5.3.6 Programming the PLL, and 5.5.1 PLL Control Register.), controls the
hardware center-of-range frequency, f_VRS. VRS7–VRS0 cannot be written when the PLLON bit in the
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
75