MC68HC908GP32_08 Datasheet, PDF (48/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Power Modes
3.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
3.4 Central Processor Unit (CPU)
3.4.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
3.4.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
3.5 Clock Generator Module (CGM)
3.5.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off
the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications that require the PLL to wake the
MCU from wait mode also can deselect the PLL output without turning off the PLL.
3.5.2 Stop Mode
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then the STOP instruction disables
the CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop is shut off but the
oscillator will continue to operate in stop mode.
3.6 Computer Operating Properly Module (COP)
3.6.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the
COP counter in a CPU interrupt routine.
MC68HC908GP32 Data Sheet, Rev. 10
48
Freescale Semiconductor