MC68HC908GP32_08 Datasheet, PDF (197/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Interrupts
TBR2:TBR0 — Timebase Rate Selection
These read/write bits are used to select the rate of timebase interrupts as shown in Table 16-1.
Table 16-1. Timebase Rate Selection for OSC1 = 32.768-kHz
TBR2
0
0
0
0
1
1
1
1
TBR1
0
0
1
1
0
0
1
1
TBR0
0
1
0
1
0
1
0
1
Divider
32768
8192
2048
128
64
32
16
8
Timebase Interrupt Rate
Hz
ms
1
1000
4
250
16
62.5
256
~ 3.9
512
~2
1024
~1
2048
~0.5
4096
~0.24
NOTE
Do not change TBR2:TBR0 bits while the timebase is enabled
(TBON = 1).
TACK — Timebase ACKnowledge
The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the
timebase interrupt flag bit. Writing a logic 0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
TBIE — Timebase Interrupt Enabled
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
TBON — Timebase Enabled
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s
16.5 Interrupts
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2:TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
197