MC68HC908GP32_08 Datasheet, PDF(111/266 Page) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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MC68HC908GP32_08 Datasheet, PDF (111/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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Chapter 11

Low-Voltage Inhibit (LVI)

11.1 Introduction

This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin

and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.

11.2 Features

Features of the LVI module include:

â¢ Programmable LVI reset

â¢ Selectable LVI trip voltage

â¢ Programmable stop mode operation

11.3 Functional Description

Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module

contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD,

enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI

module to generate a reset when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop mode

bit, LVISTOP, enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3,

enables the trip point voltage, VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit

enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The actual trip points are shown

in Chapter 19 Electrical Specifications.

NOTE

After a power-on reset (POR) the LVIâs default mode of operation is 3 V. If

a 5-V system is used, the user must set the LVI5OR3 bit to raise the trip

point to 5-V operation. Note that this must be done after every power-on

reset since the default will revert back to 3-V mode after each power-on

reset. If the VDD supply is below the 5-V mode trip voltage but above the

3-V mode trip voltage when POR is released, the part will operate because

VTRIPF defaults to 3-V mode after a POR. So, in a 5-V system care must be

taken to ensure that VDD is above the 5-V mode trip voltage after POR is

released.

NOTE

If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on

reset while the VDD supply is not above the VTRIPR for 5-V mode, the MCU

will immediately go into reset. The LVI in this case will hold the part in reset

until either VDD goes above the rising 5-V trip point, VTRIPR, which will

release reset or VDD decreases to approximately 0 V which will re-trigger

the power-on reset and reset the trip point to 3-V operation.

MC68HC908GP32 Data Sheet, Rev. 10

Freescale Semiconductor

111

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