MC68HC908GP32_08 Datasheet, PDF (152/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Serial Communications Interface Module (SCI)
FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
BYTE 3
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 3
BYTE 4
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
BYTE 3
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 3
BYTE 4
Figure 13-13. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
13.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
MC68HC908GP32 Data Sheet, Rev. 10
152
Freescale Semiconductor