MC68HC908GP32_08 Datasheet, PDF (176/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Serial Peripheral Interface Module (SPI)
15.4 Functional Description
Figure 15-1 summarizes the SPI I/O registers and Figure 15-2 shows the structure of the SPI module.
Addr. Register Name
Read:
$0010 SPI Control Register (SPCR) Write:
Reset:
$0011
Read:
SPI Status and Control
Register (SPSCR)
Write:
Reset:
$0012
Read:
SPI Data Register _Write:
(SPDR)
Reset:
Bit 7
SPRIE
0
SPRF
0
R7
T7
6
5
R
SPMSTR
0
ERRIE
1
OVRF
0
0
R6
R5
T6
T5
= Unimplemented
4
3
2
CPOL CPHA SPWOM
0
MODF
1
SPTE
0
MODFEN
0
1
0
R4
R3
R2
T4
T3
T2
Unaffected by reset
R
= Reserved
Figure 15-1. SPI I/O Register Summary
1
SPE
0
SPR1
0
R1
T1
Bit 0
SPTIE
0
SPR0
0
R0
T0
The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral
devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be
interrupt-driven.
If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. (See
12.4.3 Port C Input Pullup Enable Register.)
The following paragraphs describe the operation of the SPI module.
15.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. (See 15.13.1 SPI Control Register.)
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers
to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. (See Figure 15-3.)
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
(See 15.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control
register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the
SPTE bit.
MC68HC908GP32 Data Sheet, Rev. 10
176
Freescale Semiconductor