MC68HC908GP32_08 Datasheet, PDF (82/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Configuration Register (CONFIG)
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC
Write:
STOP
Reset: 0
0
0
0
See Note
0
0
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Figure 6-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the
OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful
for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See 3.5
Clock Generator Module (CGM) subsection 3.5.2 Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at
which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See Chapter 7 Computer Operating
Properly (COP).)
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP. (See
3.5.2 Stop Mode.)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module. (See Chapter 11 Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Chapter 11 Low-Voltage Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
MC68HC908GP32 Data Sheet, Rev. 10
82
Freescale Semiconductor