MC68HC908GP32_08 Datasheet, PDF (126/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Input/Output (I/O) Ports
Figure 12-15 shows the port D I/O logic.
NOTE
For those devices packaged in a 40-pin dual in-line package, PTD6 and
PTD7 are not connected. DDRD6 and DDRD7 should be set to a 1 to
configure PTD6 and PTD7 as outputs.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
V_DD
DDRDx
PTDx
PTDPUEx
READ PTD ($0003)
INTERNAL
PULLUP
DEVICE
PTDx
Figure 12-15. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-5 summarizes the operation of the port D pins.
Table 12-5. Port D Pin Functions
PTDPUE Bit DDRD Bit PTD Bit I/O Pin Mode
1
0
X⁽¹⁾
Input, V_DD(4)
0
0
X
Input, Hi-Z⁽²⁾
X
1
X
Output
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V_DD by internal pullup device.
Accesses to DDRD
Read/Write
DDRD7–DDRD0
DDRD7–DDRD0
DDRD7–DDRD0
Accesses to PTD
Read
Write
Pin
PTD7–PTD0⁽³⁾
Pin
PTD7–PTD0⁽³⁾
PTD7–PTD0
PTD7–PTD0
MC68HC908GP32 Data Sheet, Rev. 10
126
Freescale Semiconductor