MC68HC908GP32_08 Datasheet, PDF (159/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

SIM Bus Clock Control and Generation
Addr.
$FE03
$FE04
$FE05
$FE06
Register Name
Read:
SIM Break Flag Control
Register (SBFCR)
Write:
Reset:
Read:
Interrupt Status Register 1
(INT1)
Write:
Reset:
Read:
Interrupt Status Register 2
(INT2)
Write:
Reset:
Read:
Interrupt Status Register 3
(INT3)
Write:
Reset:
Bit 7
BCFE
0
IF6
R
0
IF14
R
0
0
R
0
6
5
R
R
IF5
IF4
R
R
0
0
IF13
IF12
R
R
0
0
0
0
R
R
0
0
= Unimplemented
4
3
2
R
R
R
IF3
IF2
IF1
R
R
R
0
0
0
IF11
IF10
IF9
R
R
R
0
0
0
0
0
0
R
R
R
0
0
0
R = Reserved
Figure 14-2. SIM I/O Register Summary (Continued)
1
Bit 0
R
R
0
0
R
R
0
0
IF8
IF7
R
R
0
0
IF16
IF15
R
R
0
0
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 14-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 5 Clock Generator Module
(CGM).)
OSC2
OSC1
OSCILLATOR (OSC)
CGMXCLK
TO TIMTB15A, ADC
OSCSTOPENB
FROM
CONFIG
CGMRCLK
PHASE-LOCKED LOOP (PLL)
CGMOUT
SIM
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF CHIP
IT23
TO REST
OF CHIP
SIMDIV2
Figure 14-3. CGM Clock Signals
MONITOR MODE
USER MODE
PTC3
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
159