MC68HC908GP32_08 Datasheet, PDF (147/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Control Bits
M PEN and PTY
0
0X
1
0X
0
10
0
11
1
10
1
11
Table 13-5. Character Format Selection
Start Bits
1
1
1
1
1
1
Data Bits
8
9
7
7
8
8
Character Format
Parity Stop Bits
None
1
None
1
Even
1
Odd
1
Even
1
Odd
1
I/O Registers
Character Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
13.8.2 SCI Control Register 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
Address: $0014
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 13-10. SCI Control Register 2 (SCC2)
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset
clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears
the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
147