MC68HC908GP32_08 Datasheet, PDF (112/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Low-Voltage Inhibit (LVI)
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See 6.2
Functional Description for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU
remains in reset until V_DD rises above a voltage, V_TRIPR, which causes the MCU to exit reset. See
14.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The
output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
V_DD
LVIPWRD
FROM CONFIG
STOP INSTRUCTION
FROM CONFIG1
LVIRSTD
LVISTOP
FROM CONFIG1
LOW V_DD
DETECTOR
V_DD > LVI_Trip = 0
V_DD ≤ LVI_Trip = 1
LVI5OR3
FROM CONFIG1
LVIOUT
Figure 11-1. LVI Module Block Diagram
LVI RESET
Addr. Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
$FE0C LVI Status Register (LVISR) Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. LVI I/O Register Summary
11.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level, software can monitor V_DD by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at logic 0 to enable the LVI
module, and the LVIRSTD bit must be at logic 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls below the V_TRIPF level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
MC68HC908GP32 Data Sheet, Rev. 10
112
Freescale Semiconductor