MC68HC908GP32_08 Datasheet, PDF (139/266 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
13.4.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a
frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at
the following times (see Figure 13-6):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
PTE1/RxD
START BIT
LSB
SAMPLES
START BIT
QUALIFICATION
START BIT
DATA
VERIFICATION SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 13-6. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 13-2 summarizes the results of the start bit verification samples.
Table 13-2. Start Bit Verification
RT3, RT5, and RT7
Samples
000
001
010
011
100
101
110
111
Start Bit
Verification
Yes
Yes
Yes
No
Yes
No
No
No
Noise Flag
0
1
1
0
1
0
0
0
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
MC68HC908GP32 Data Sheet, Rev. 10
Freescale Semiconductor
139