39K30 Datasheet, PDF (9/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

All channel memory
inputs are driven from
the routing channels
4096-bit Dual-Port
Array
Configurable as
Async/Sync Dual-Port
or Sync FIFO
Configurable as
4K x 1, 2K x 2, 1K x 4,
and 512 x 8 block sizes
All channel memory outputs
drive dedicated tracks in the
routing channels
Horizontal Channel
Delta39K™ ISR™
CPLD Family
Global Clock
Signals
GCLK[3:0]
Figure 6. Block Diagram of Channel Memory Block
I/O Banks
The Delta39K interfaces the horizontal and vertical routing
channels to the pins through I/O banks. There are eight I/O
banks per device as shown in Figure 7, and all I/Os from an
I/O bank are located in the same section of a package for PCB
layout convenience.
Delta39K devices support True Vertical Migration™ (i.e., for
each package type, Delta39K devices of different densities
keep given pins in the same I/O banks). This allows for easy
and simple implementation of multiple I/O standards during the
design and prototyping phase, before a final density has been
determined. Please refer to the application note titled “Family,
Package and Density Migration in Delta 39K and Quantum38K
CPLDs.”
Each I/O bank contains several I/O cells, and each I/O cell
contains an input/output register, an output enable register,
programmable slew rate control and programmable bus hold
control logic. Each I/O cell drives a pin output of the device;
the cell also supplies an input to the device that connects to a
dedicated track in the associated routing channel.
Each I/O bank can use any supported I/O standard by
supplying appropriate V_REF and V_CCIO voltages and config-
uring the I/O through the Warp software. All the V_REF and
V_CCIO pins in an I/O bank must be connected to the same V_REF
and V_CCIO voltage respectively. This requirement restricts the
number of I/O standards supported by an I/O bank at any given
time.
The number of I/Os which can be used in each I/O bank
depend on the type of I/O standards and the number of V_CCIO
and GND pins being used. This restriction is derived from the
electromigration limit of the V_CCIO and GND bussing on the
chip. Please refer to the note on page 17 and the application
note titled “Delta39K Family Device I/O Standards and Config-
urations” for details.
I/O Cell
Figure 8 is a block diagram of the Delta39K I/O cell. The I/O
cell contains a three-state input buffer, an output buffer, and a
register that can be configured as an input or output register.
The output buffer has a slew rate control option that can be
used to configure the output for a slower slew rate. The input
of the device and the pin output can each be configured as
registered or combinatorial; however, only one path can be
configured as registered in a given design.
The output enable in an I/O cell can be selected from one of
the four global control signals or from one of two Output
Control Channel (OCC) signals. The output enable can be
configured as always enabled or always disabled or it can be
controlled by one of the remaining inputs to the mux. The
selection is done via a mux that includes V_CC and GND as
inputs.
bank 7 bank 6
D_De_el_lt_ta_a3₃9₉K_K
bank 2 bank 3
Figure 7. Delta39K I/O Bank Block Diagram
Document #: 38-03039 Rev. *H
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