39K30 Datasheet, PDF (24/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Delta39K™ ISR™
CPLD Family
Channel Memory Timing Parameter Values Over the Operating Range (continued)
Dual-Port Synchronous Mode Parameters
t_CHMCYC1
9.5
10
t_CHMCYC2
5.0
5.3
t_CHMS
3.0
3.3
t_CHMH
0
0
t_CHMDV1
10
t_CHMDV2
7.0
t_CHMBDV
8.5
t_CHMMACS1
8.5
9.0
t_CHMMACS2
4.8
5.0
t_MACCHMS1
4.6
5.0
t_MACCHMS2
7.3
7.3
Synchronous FIFO Data Parameters
10
15
20
ns
5.4
7.4
10.6
ns
3.9
5.0
6.0
ns
0
0
0
ns
11
12
17
20
ns
7.5
8.0
10
15
ns
9.0
10.0
14.0
16.0
ns
10.0
14.0
16.0
ns
5.5
8.0
10
ns
5.4
7.6
9.0
ns
7.7
10.0
13.0
ns
t_CHMCLK
4.8
5.0
5.4
7.4
10.6
ns
t_CHMFS
3.7
4.0
4.3
6.0
7.0
ns
t_CHMFH
0
0
0
0
0
ns
t_CHMFRDV
6.5
7.0
7.5
10.0
13.0
t_CHMMACS
4.6
5.0
5.4
7.4
10.6
ns
t_MACCHMS
4.7
5.0
5.4
7.4
10.6
ns
Synchronous FIFO Flag Parameters
t_CHMFO
10.5
11
11.5
15
20
ns
t_CHMMACF
8.5
9
9.5
13
17
ns
t_CHMFRS
4.5
5.0
5.5
8.0
10
ns
t_CHMFRSR
3.6
4.0
4.4
6.6
8.0
ns
t_CHMFRSF
9.5
10.0
11.0
15.0
18.0
ns
t_CHMSKEW1
1.8
2.0
2.2
3.2
4.0
ns
t_CHMSKEW2
1.8
2.0
2.2
3.2
4.0
ns
t_CHMSKEW3
4.6
5.0
5.4
7.4
10.6
ns
Internal Parameters
t_CHMCHAA
6.5
7.0
7.5
10.0
13.0
ns
Switching Waveforms
Combinatorial Output
INPUT
t_PD
COMBINATORIAL
OUTPUT
Document #: 38-03039 Rev. *H
Page 24 of 86