39K30 Datasheet, PDF (37/86 Pages) Cypress Semiconductor – CPLDs at FPGA DensitiesTM

Switching Waveforms (continued)
Channel Memory Synchronous FIFO Master Reset Timing
MASTER
RESET INPUT
t_CHMFRS
t_CHMFRSR
READ ENABLE /
WRITE ENABLE
EMPTY/FULL
PROGRAMMABLE
ALMOST EMPTY
FLAGS
t_CHMFRSF
t_CHMFRSF
HALF-FULL/
PROGRAMMABLE
ALMOST FULL
FLAGS
t_CHMFRSF
REGISTERED
OUTPUT
Delta39K™ ISR™
CPLD Family
CY 39 100 V 676 - 200 MB C
Cypress Semiconductor ID
Family Type
39 = Delta39K Family
Gate Density
30=30k Usable Gates
50=50k Usable Gates
100=100k Usable Gates
165 = 165k Usable Gates
200 = 200k Usable Gates
Operating Reference Voltage
V = 3.3V or 2.5V Supply Voltage
Z = 1.8V
Supply Voltage
Pin Count
208 = 208 Leads
256 = 256 Balls
388 = 388 Balls
484 = 484 Balls
676 = 676 Balls
Operating Conditions
Commercial
0°C to +70°C
Industrial
--40°C to +85°C
Package Type
N = Plastic Quad Flat Pack (PQFP)
NT = Thermally Enhanced Quad Flat Pack (EQFP)
BG = Ball Grid Array (BGA)
BB = Fine-pitch Ball Grid Array (FBGA)
1.0-mm Lead Pitch
MG = Self-Boot Solution -- Ball Grid Array
MB = Self-Boot Solution -- Fine Pitch Ball Grid Array
1.0-mm Lead Pitch
Speed
233 = 233 MHz
200 = 200 MHz
181 = 181 MHz
125 = 125 MHz
83 = 83 MHz
Document #: 38-03039 Rev. *H
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